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? semiconductor components industries, llc, 2007 january, 2007 ? rev. 0 1 publication order number: ncp5218/d ncp5218 2?in?1 notebook ddr power controller the ncp5218 2 ? in ? 1 notebook ddr power controller is specifically designed as a total power solution for notebook ddr memory system. this ic combines the efficiency of a pwm controller for the v ddq supply with the simplicity of linear regulators for the v tt termination voltage and the buffered low noise reference. this ic contains a synchronous pwm buck controller for driving two external nfets to form the ddr memory supply voltage (v ddq ). the ddr memory termination regulator output voltage (v tt ) and the buffered v ref are internally set to track at the half of v ddq . an internal power good voltage monitor tracks v ddq output and notifies the user whether the v ddq output is within target range. protective features include soft ? start circuitries, undervoltage monitoring of supply voltage, v ddq overcurrent protection, v ddq overvoltage and undervoltage protections, and thermal shutdown. the ic is packaged in dfn22. features ? incorporates v ddq , v tt regulator, buffered v ref ? adjustable v ddq output ? v tt and v ref track v ddq /2 ? operates from single 5.0 v supply ? supports v ddq conversion rails from 4.5 v to 24 v ? power ? saving mode for high efficiency at light load ? integrated power fets with v tt regulator sourcing/sinking 1.5 a dc and 2.4 a peak current ? requires only 20 f ceramic output capacitor for v tt ? buffered low noise 15 ma v ref output ? all external power mosfets are n ? channel ? <5.0 a current consumption during shutdown ? fixed switching frequency of 400 khz ? soft ? start protection for v ddq and v tt ? undervoltage monitor of supply voltage ? overvoltage protection and undervoltage protection for v ddq ? short ? circuit protection for v ddq and v tt ? thermal shutdown ? housed in dfn22 ? this is a pb ? free device typical applications ? notebook ddr/ddr2 memory supply and termination voltage ? active termination busses (sstl ? 18, sstl ? 2, sstl ? 3) dfn22 mn suffix case 506af pin connections device package shipping ? ordering information NCP5218MNR2G dfn22 (pb ? free) 2500 tape & reel ncp5218= specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package marking diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. http://onsemi.com vddqen vtten fpwm ss vttgnd vtt vtti fbvtt agnd ddqref vcca pgnd bgddq vccp swddq tgddq boost ocddq pgood vttref fbddq comp (top view) note: pin 23 is the thermal pad on the bottom of the device. ncp5218 awlyyww 1 1 22
ncp5218 http://onsemi.com 2 vddqen vddqen vtten vtten fpwm fpwm ss css pgood 5vcc vtt vtt cout2 ceramic 10 f x2 0.9 v, 1.5 a vtt vtt vtt fbvtt vttgnd vcca 5vcc ddqref agnd rl1 ocddq boost vccp tgddq m1 swddq m2 pgnd1 comp fbddq cz1 rz1 cp1 cz2 rz2 r1 r2 vtti bgddq vddq 1.8 v, 10 a l 1.8 h vin 4.5 v to 24 v (battery/ adapter) 5vcc ncp5218 figure 1. typical application diagram pwrgd cout1 poscap 150 f x2 vttref vref 0.9 v, 15 ma
ncp5218 http://onsemi.com 3 5vcc vddqen vtten vcca vcca voltage & current reference vref vrefgd control logic ? + vref vccagd fault tsd thermal shutdown vccp vccp vin cbulk 5vcc vboost boost inregddq vddq pwm logic power ? saving loop control ? + ilim fbddq swddq rl1 cdcpl ocddq cboost cout1 vddq l ? + vccp negative current detection pgnd m3 m4 tgddq vboost swddq bgddq pgnd ? + uvlo vfbddq vref ? + vref vfbddq ovlo ? + ? + a vref comp fbddq cz2 cp1 cz1 rz2 rz1 r1 r2 ddqref vtti vtt vtt cout2 m1 m2 vttgnd fbvtt vttgnd vcca vttgnd vcca vttgnd vtt regulation control vddqen vtten ss 5vcc pgood pgnd osc adaptive ramp vocddq current limit & soft ? start ? + sc2pwr vddqen vtten inregddq ? + sc2gnd gnd agnd figure 2. detailed block diagram pwm ? comp iref vddqen vtten vocddqgd fpwm fpwm deadband control ? + vtti vttref vttref cout3 vttgnd pgnd ? + vocddq vref vcca
ncp5218 http://onsemi.com 4 pin function description pin symbol description 1 vddqen v ddq regulator enable input. high to enable. 2 vtten v tt regulator enable input. high to enable. 3 fpwm forced pwm enable input. low to enable forced pwm mode and disable power ? saving mode. 4 ss v ddq soft ? start capacitor connection to ground. 5 vttgnd power ground for the v tt regulator. 6 vtt v tt regulator output. 7 vtti power input for v tt regulator which is normally connected to the v ddq output of the buck regulator. 8 fbvtt v tt regulator feedback pin for closed loop regulation. 9 agnd analog ground connection and remote ground sense. 10 ddqref external reference input which is used to regulate v tt and v ttref to 1/2v ddqref . 11 vcca 5.0 v supply input for the ic?s control and logic section, which is monitored by undervoltage lock out circuitry. 12 comp v ddq error amplifier compensation node. 13 fbddq v ddq regulator feedback pin for closed loop regulation. 14 vttref ddr reference voltage output. 15 pgood power good signal open ? drain output. 16 ocddq overcurrent sense and program input for the high ? side fet of v ddq regulator. also the battery voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input voltage variation. this pin must be connected to the v in through a resistor to perform the current limit and voltage feedforward functions. 17 boost positive supply input for high ? side gate driver of v ddq regulator and boost capacitor connection. 18 tgddq gate driver output for v ddq regulator high ? side n ? channel power fet. 19 swddq v ddq regulator inductor driven node, return for high ? side gate driver, and current limit sense input. 20 vccp power supply for the v ddq regulator low ? side gate driver and also supply voltage for the bootstrap capacitor of the v ddq regulator high ? side gate driver supply. 21 bgddq gate driver output for v ddq regulator low ? side n ? channel power fet. 22 pgnd power ground for the v ddq regulator. 23 thpad copper pad on bottom of ic used for heatsinking. this pin should be connected to the ground plane under the ic.
ncp5218 http://onsemi.com 5 maximum ratings rating symbol value unit power supply v oltage (pin 11, 20) to agnd (pin 9) v cca , v ccp ? 0.3, 6.0 v high ? side gate drive supply: boost (pin 17) to swddq (pin 19) v boost ? v swddq ? 0.3, 6.0 v input/output pins to agnd (pin 9) pins 1 ? 4, 6 ? 8, 10, 12 ? 15 v io ? 0.3, 6.0 v overcurrent sense input (pin 16) to agnd (pin 9) v ocddq 27 v switch node (pin 19) v swddq ? 4.0 (<100 ns), ? 0.3 (dc), 32 v high ? side fet gate drive voltage: tgddq (pin 18) to swddq (pin 19) v tgddq ? v swddq ? 2.0 (< 100 ns) ? 0.3 (dc), 6.0 v low ? side fet gate drive voltage: bgddq (pin 21) to pgnd (pin 22) v bgddq ? 2.0 (< 100 ns) ? 0.3 (dc), 6.0 v pgnd (pin 22), vttgnd (pin 5) to agnd (pin 9) v gnd ? 0.3, 0.3 v thermal characteristics dfn22 plastic package thermal resistance, junction ? to ? ambient r ja 35 c/w operating junction temperature range t j 0 to +150 c operating ambient temperature range t a ? 40 to +85 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114 except pin 17 which is 1 kv. machine model (mm) 200 v per jedec standard: jesd22?a115 except pin 17 which is 150 v. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78. 3. pin 16 (ocddq) must be pulled high to v in through a resistor.
ncp5218 http://onsemi.com 6 electrical characteristics (v in = 12 v, t a = ? 40 to 85 c, v cca = v ccp = v boost ? v swddq = 5.0 v, l = 1.8 h, c out1 = 150 f x 2, c out2 = 22 f x 2, rl1 = 5.6 k , r1 = 4.3 k , r2 = 3.3 k , rz1 = 10 k , rz2 = 130 , cp1 = 100 pf, cz1 = 2.2 nf, cz2 = 4.7 nf, for min/max values unless otherwise noted. typical values are at t a = 25 c.) characteristic symbol test conditions min typ max unit supply voltage input v oltage v in ? 4.5 ? 24 v v cca operating v oltage v cca ? 4.5 5.0 5.5 v v ccp operating v oltage v ccp ? 4.5 5.0 5.5 v supply current v cca quiescent supply current in s0 i vcca_s0 v ddqen = 5.0 v, v tten = 5.0 v ? 3.5 10 ma v cca quiescent supply current in s3 i vcca_s3 v ddqen = 5.0 v, v tten = 0 v ? 0.9 5.0 ma v cca shutdown current i vcca_sd v ddqen = 0 v, v tten = 0 v, t a = 25 c ? 1.0 4.0 a v ccp quiescent supply current in s0 i vccp_s0 v ddqen = 5.0 v, v tten = 5.0 v, tgddq and bgddq open ? ? 20 ma v ccp quiescent supply current in s3 i vccp_s3 v ddqen = 5.0 v, v tten = 0 v, tgddq and bgddq open ? ? 20 ma v ccp shutdown current i vccp_sd v ddqen = 0 v, v tten = 0 v ? 1.0 2.0 a undervoltage monitor v cca uvlo lower threshold v ccauv ? falling edge ? 3.7 4.1 v v cca uvlo hysteresis v ccauvhys ? ? 0.35 ? v v ocddq uvlo upper threshold v ocddquv+ rising edge ? 3.0 4.4 v v ocddq uvlo hysteresis v ocddquvhys ? ? 0.4 ? v thermal shutdown thermal trip point t sd (note 4) ? 150 ? c hysteresis t sdhys (note 4) ? 25 ? c v ddq switching regulator fbddq feedback v oltage, control loop in regulation v fbddq t a = 25 c t a = ? 40 to 85 c 0.788 0.784 0.8 0.8 0.812 0.816 v feedback input current i fb v fbddq = 0.8 v ? ? 1.0 a oscillator frequency f sw ? 340 400 460 khz ramp amplitude v oltage v ramp v in = 5.0 v (note 4) ? 1.25 ? v ramp amplitude to v in ratio d vramp /d vin ? ? 45 ? mv/v ocddq pin current sink i oc v ocddq = 4.0 v 26 31 36 a ocddq pin current sink temperature coef ficient tc ioc t a = ? 40 to 85 c ? 3200 ? ppm/ c minimum on time t onmin ? ? 150 ? ns maximum duty cycle d max v in = 5.0 v v in = 15 v v in = 24 v ? ? ? 90 50 32 ? ? ? % soft ? start current i ss v ddqen = 5.0 v, vss = 0 v 2.8 4.0 5.2 a overvoltage trip threshold fbovp th with respect to error comparator threshold of 0.8 v 115 130 ? % undervoltage trip threshold fbuvp th with respect to error comparator threshold of 0.8 v ? 65 75 % 4. guaranteed by design, not tested in production.
ncp5218 http://onsemi.com 7 electrical characteristics (continued) (v in = 12 v, t a = ? 40 to 85 c, v cca = v ccp = v boost ? v swddq = 5.0 v, l = 1.8 h, c out1 = 150 f x 2, c out2 = 22 f x 2, rl1 = 5.6 k , r1 = 4.3 k , r2 = 3.3 k , rz1 = 10 k , rz2 = 130 , cp1 = 100 pf, cz1 = 2.2 nf, cz2 = 4.7 nf, for min/max values unless otherwise noted. typical values are at t a = 25 c.) characteristic symbol test conditions min typ max unit error amplifier dc gain gain (note 5) ? 70 ? db unity gain bandwidth f t comp_gnd = 220 nf, 1.0 in series (note 5) ? 2.0 ? mhz slew rate s r (note 5) ? 3.0 ? v/ s gate drivers tgddq gate pull ? high resistance r h_tg v boost ? v swddq = 5.0 v, v tgddq ? v swddq = 4.0 v ? 1.8 4.0 tgddq gate pull ? low resistance r l_tg v boost ? v swddq = 5.0 v, v tgddq ? v swddq = 1.0 v ? 1.8 4.0 bgddq gate pull ? high resistance r h_bg v ccp = 5.0 v, v bgddq = 4.0 v ? 1.8 4.0 bgddq gate pull ? low resistance r l_bg v ccp = 5.0 v, v bgddq = 1.0 v ? 0.9 3.0 v tt active terminator v tt with respect to 1/2v ddqref d vtt0 1/2v ddqref ? v tt , v ddqref = 2.5 v, i vtt = 0 to 2.4 a (sink current) i vtt = 0 to ?2.4 a (source current) ? 30 ? ? ? ? 30 mv 1/2v ddqref ? v tt , v ddqref = 1.8 v, i vtt = 0 to 2.0 a (sink current) i vtt = 0 to ?2.0 a (source current) ? 30 ? ? ? ? 30 mv ddqref input resistance ddqref_r v ddqref = 2.5 v 40 55 75 k source current limit i limvtsrc ? 2.5 3.0 ? a sink current limit i limvtsnk ? 2.5 3.0 ? a soft ? start source current limit i limvtss ? ? 1.0 ? a maximum soft ? start time t ssvttmax ? ? 0.32 ? ms v ttref output v ttref source current i vttr v ddqref = 1.8 v or 2.5 v 15 ? ? ma v ttref accuracy referred to 1/2v ddqref d vttr 1/2v ddqref ? v ttr , v ddqref = 2.5 v, i vttr = 0 ma to 15 ma ? 25 ? 25 mv 1/2v ddqref ? v ttr , v ddqref = 1.8 v, i vttr = 0 ma to 15 ma ? 18 ? 18 mv 5. guaranteed by design, not tested in production.
ncp5218 http://onsemi.com 8 electrical characteristics (continued) (v in = 12 v, t a = ? 40 to 85 c, v cca = v ccp = v boost ? v swddq = 5.0 v, l = 1.8 h, c out1 = 150 f x 2, c out2 = 22 f x 2, rl1 = 5.6 k , r1 = 4.3 k , r2 = 3.3 k , rz1 = 10 k , rz2 = 130 , cp1 = 100 pf, cz1 = 2.2 nf, cz2 = 4.7 nf, for min/max values unless otherwise noted. typical values are at t a = 25 c.) characteristic symbol test conditions min typ max unit control section vddqen pin threshold high v ddqen_h ? 1.4 ? ? v vddqen pin threshold low v ddqen_l ? ? ? 0.5 v vddqen pin input current i in_ vddqen v ddqen = 5.0 v ? ? 1.0 a vtten pin threshold high v tten_h ? 1.4 ? ? v vtten pin threshold low v tten_l ? ? ? 0.5 v vtten pin input current i in_vtten v ddqen = v tten = 5.0 v ? ? 1.0 a fpwm pin threshold high fpwm _h ? 1.4 ? ? v fpwm pin threshold low fpwm _l ? ? ? 0.5 v fpwm pin input current i in_fpwm v ddqen = v tten =fpwm = 5.0 v ? ? 1.0 a pgood pin on resistance pgood_r i _pgood = 5.0 ma ? 70 ? pgood pin off current pgood_lk ? ? ? 1.0 a pgood low ? to ? high hold time, for s5 to s0 t hold (note 6) ? ? 200 s 6. guaranteed by design, not tested in production.
ncp5218 http://onsemi.com 9 figure 3. vcca quiescent current in s0 vs. ambient temperature figure 4. vcca quiescent current in s3 vs. ambient temperature figure 5. vcca shutdown current vs. ambient temperature figure 6. switching frequency in s0 vs. ambient temperature figure 7. v ddq feedback voltage vs. ambient temperature figure 8. soft ? start current vs. ambient temperature typical operating characteristics 3.0 3.2 3.4 3.6 3.8 4.0 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) i vcca_s0 , quiescent current in s0 (ma) 60 0.0 0.2 0.4 0.6 0.8 1.0 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) i vcca_s3 , quiescent current in s3 (ma) 60 0 2 4 6 8 10 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) i vcca_sd , shutdown current ( a) 60 350 375 400 425 450 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) f sw , switching frequency in s0 (khz) 60 0.70 0.75 0.80 0.85 0.90 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) v fbddq , vddq feedback voltage (v) 60 3.0 3.5 4.0 4.5 5.0 ? 40 ? 15 10 35 85 t a , ambient temperature ( c) i ss , soft ? start current ( a) 60
ncp5218 http://onsemi.com 10 figure 9. vddq output voltage vs. input voltage figure 10. vddq output voltage vs. vddq output current figure 11. vtt output voltage (ddr) vs. vtt output current figure 12. vtt output voltage (ddr2) vs. vtt output current figure 13. vttr output voltage (ddr) vs. vttr output current figure 14. vttr output voltage (ddr2) vs. vttr output current typical operating characteristics 1.780 1.785 1.790 1.795 1.800 1.805 0 5 10 15 25 v in , input voltage (v) v ddq , vddq output voltage (v) 20 1.790 1.795 1.800 1.805 1.810 02 46 10 i vddq , vddq output current (a) v ddq , vddq output voltage (v) 8 1.21 1.22 1.23 1.24 1.25 1.26 ? 3.0 ? 2.0 ? 1.0 0.0 3.0 i vtt , vtt output current (a) v tt , vtt output voltage (v) 1.0 1.240 1.245 1.250 1.255 1.260 0 5 10 15 i vttr , vttr output current (ma) v ttr , vttr output voltage (v) 1.810 1.815 1.820 i vddq = 100 ma i vddq = 10 a v ddq = 1.8 v s0 mode t a = 25 c v in = 24 v v ddq = 1.8 v t a = 25 c v in = 5 v 2.0 1.27 1.28 1.29 v in = 24 v v ddq = 2.5 v t a = 25 c v in = 5 v 0.86 0.87 0.88 0.89 0.90 0.91 ? 1.5 ? 1.0 ? 0.5 0.0 1.5 i vtt , vtt output current (a) v tt , vtt output voltage (v) 0.5 1.0 0.92 0.93 0.94 v in = 24 v v ddq = 1.8 v t a = 25 c v in = 5 v ? 2.0 2.0 v in = 24 v v ddq = 2.5 v t a = 25 c v in = 5 v 0.890 0.895 0.900 0.905 0.910 0 5 10 15 i vttr , vttr output current (ma) v ttr , vttr output voltage (v) v in = 24 v v ddq = 1.8 v t a = 25 c v in = 5 v
ncp5218 http://onsemi.com 11 figure 15. v ddq efficiency (ddr) vs. v ddq output current figure 16. v ddq efficiency (ddr2) vs. v ddq output current figure 17. powerup waveforms figure 18. powerdown waveforms figure 19. v ddq , v ttr startup w aveforms figure 20. v ddq , v ttr shutdown waveforms typical operating characteristics 50 60 70 80 90 100 0.1 1.0 10 100 i vddq , vddq output current (a) efficiency of vddq (%) v in = 20 v v ddq = 2.5 v freq = 400 khz max t a = 25 c v in = 12 v v in = 5 v with power ? saving without power ? saving 50 60 70 80 90 100 0.1 1.0 10 100 i vddq , vddq output current (a) efficiency of vddq (%) v in = 20 v v ddq = 1.8 v freq = 400 khz max t a = 25 c v in = 12 v v in = 5 v with power ? saving without power ? saving vddq vin vtt vttr 20v/div 1v/div 1v/div 1v/div vddqen = high; vtten = high; vin = 0 v to 20 v vin vddq vtt vttr 20v/div 1v/div 1v/div 1v/div vddqen = high; vtten = high; vin =20 v to 0 v vddqen vddq vttr pgood 5v/div 1v/div 1v/div 5v/div vddqen = 0 v to 5 v vddqen vddq vttr pgood 5v/div 5v/div 1v/div 1v/div vddqen = 5 v to 0 v
ncp5218 http://onsemi.com 12 figure 21. v tt startup w aveforms figure 22. v tt shutdown waveforms figure 23. s0 ? s3 ? s0 transition w aveforms figure 24. ps ? fpwm ? ps transition waveforms figure 25. v ddq load transient figure 26. v ddq load transient typical operating characteristics vtten vtt ivtti 5v/div 1v/div 500ma/div vddqen = high; vtt loaded with 4.7 to gnd vtten vtt ivtti 5v/div 1v/div 500ma/div vddqen = high; vtt loaded with 4.7 to gnd vddq vtt vttr vtten ivddq = 50 ma, ivtt = 100 ma, ivttr = 5 ma 100mv/div 50mv/div 1v/div 5v/div vddq vtt vttr fpwm 100mv/div 1v/div 50mv/div 5v/div ivddq = 50ma, ivtt = 100ma, ivttr = 5ma, vtten = 0v ivddq = 0 a ? 7 a, ivtt = 1.5 a, ivttr = 15 ma vddq vtt vttr ivddq 100mv/div 50mv/div 50mv/div 5a/div ivddq = 7 a ? 0 a, ivtt = 1.5 a, ivttr = 15 ma vddq vtt vttr ivddq 100mv/div 50mv/div 50mv/div 5a/div
ncp5218 http://onsemi.com 13 figure 27. v tt source current t ransient figure 28. v tt sink current transient figure 29. line transient 7 v to 20 v at no load figure 30. line transient 20 v to 7 v at no load figure 31. line transient 7 v to 20 v at full load figure 32. line transient 20 v to 7 v at full load typical operating characteristics ivddq = 8 a, ivtt = 0 a to 2 a to 0 a, ivttr = 15 ma vddq vtt vttr ivtt 100mv/div 50mv/div 50mv/div 2a/div ivddq = 8 a, ivtt = 0 a to ? 2 a to 0 a, ivttr = 15 ma vddq vttr vtt ivtt 50mv/div 50mv/div 2a/div 100mv/div ivddq = 0 a, ivtt = 0 a, ivttr = 0 ma, vin = 7 v to 20 v vddq vtt vttr vin 100mv/div 50mv/div 50mv/div 10v/div ivddq = 0 a, ivtt = 0 a, ivttr = 0 ma, vin = 20 v to 7 v vddq vtt vttr vin 100mv/div 50mv/div 50mv/div 10v/div ivddq = 10a, ivtt = 1.5a, ivttr = 15ma, vin = 7v to 20v vddq vtt vttr vin 100mv/div 50mv/div 50mv/div 10v/div ivddq = 10a, ivtt = 1.5a, ivttr = 15ma, vin = 20v to 7v vddq vtt vttr vin 10v/div 50mv/div 50mv/div 100mv/div
ncp5218 http://onsemi.com 14 figure 33. v tt short circuit to ground and recovery figure 34. v tt short circuit to vddq and recovery figure 35. v ddq ocp by short circuit to ground figure 36. v ddq ocp by steady ivddq increase figure 37. v ddq ocp by start into a short circuit typical operating characteristics vddq vtt vttr ivtt ivddq = 8 a, vtt shorts to ground, ivttr = 15 ma 100mv/div 1v/div 5a/div ivddq = 8 a, vtt shorts to vddq, ivttr = 15 ma vddq vtt vttr ivtt 100mv/div 1v/div 50mv/div 5a/div vddq, 1v/div vin, 20v/div vswddq, 10v/div il, 10a/div vddq, 1v/div vin, 20v/div vswddq, 10v/div il, 10a/div vswddq, 10v/div vddq, 1v/div il, 10a/div vin, 20v/div 50mv/div
ncp5218 http://onsemi.com 15 detailed operating description general the ncp5218 2 ? in ? 1 notebook ddr power controller combines the efficiency of a pwm controller for the v ddq supply, with the simplicity of using a linear regulator for the v tt termination voltage power supply. the v ddq output can be adjusted through the external potential divider, while the v tt is internally set to track half v ddq . the inclusion of v ddq power good voltage monitor, soft ? start, v ddq overcurrent protection, v ddq overvoltage and undervoltage protections, supply undervoltage monitor, and thermal shutdown makes this device a total power solution for high current ddr memory system. the ic is packaged in dfn22. control logic the internal control logic is powered by vcca. the ic is enabled whenever v ddqen is high (exceed 1.4 v). an internal bandgap voltage, v ref , is then generated. once v ref reaches its regulation voltage, an internal signal v refgd will be asserted. this transition wakes up the supply undervoltage monitor blocks, which will assert vccagd if vcca voltage is within certain preset levels. the control logic accepts external signals at vcca, ocddq, vddqen, vtten, and fpwm pins to control the operating state of the v ddq and v tt regulators in accordance with table 1. a timing diagram is shown in figure 38. v ddq switching regulator in normal mode (s0) the v ddq regulator is a switching synchronous rectification buck controller directly driving two external n ? channel power fets. an external resistor divider sets the nominal output voltage. the control architecture is voltage mode fixed frequency pwm with external compensation and with switching frequency fixed at 400 khz 15%. as can be observed from figure 1, the v ddq output voltage is divided down and fed back to the inverting input of an internal error amplifier through fbddq pin to close the loop at v ddq = v fbddq (1 + r1/r2). this amplifier compares the feedback voltage with an internal v ref (= 0.800 v) to generate an error signal for the pwm comparator. this error signal is further compared with a fixed frequency ramp waveform derived from the internal oscillator to generate a pulse ? width ? modulated signal. this pwm signal drives the external n ? channel power fets via the tgddq and bgddq pins. external inductor l and capacitor c out1 filter the output waveform. the v ddq output voltage ramps up at a pre ? defined soft ? start rate when the ic enters state s0 from s5. when in normal mode, and regulation of v ddq is detected, signal in regddq will go high to notify the control logic block. input voltage feedforward is implemented to the ramp signal generation to reject the effect of wide input voltage variation. with input voltage feedforward, the amplitude of the ramp is proportional to the input voltage. for enhanced ef ficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or schottky diode rectifier. adaptive nonoverlap timing control of the complementary gate drive output signals is provided to reduce large shoot ? through current that degrades efficiency. tolerance of v ddq the tolerance of v fbddq and the ratio of external resistor divider r1/r2 both impact the precision of v ddq . with the control loop in regulation, v ddq = v fbddq (1 + r1/r2). with a worst case (for all valid operating conditions) v fbddq tolerance of 1.5%, a worst case range of 2.5% for v ddq = 1.8 v will be assured if the ratio r1/r2 is specified as 1.2500 1%. table 1. state, operation, input and output condition table mode input conditions operating conditions output conditions vcca vocddq vddqen vtten fpwm vddq vttref vtt tgddq bgddq pgood s5 low x x x x h ? z h ? z h ? z low low low s5 x low x x x h ? z h ? z h ? z low low low s0 high high high high x normal normal normal normal normal h ? z s3 high high high low high standby normal h ? z standby (power ? saving) standby (power ? saving) h ? z s3 high high high low low normal normal h ? z normal normal h ? z s5 x x low x x h ? z h ? z h ? z low low low v ddq regulator in standby mode (s3) during state s3, a power ? saving mode is activated when the fpwm pin is pulled to vcca. in power ? saving mode, the switching frequency is reduced with the v ddq output current and the low ? side fet is turned off after the detection of negative inductor current, so as to enhance the
ncp5218 http://onsemi.com 16 efficiency of the v ddq regulator at light loads. the switching frequency can be reduced smoothly until it reaches the minimum frequency at about 15 khz. therefore, perceptible audible noise can be avoided at light load condition. in power ? saving mode, the low ? side mosfet is turned off after the detection of negative inductor current and the converter cannot sink current. the power ? saving mode can be disabled by pulling the fpwm pin to ground. then, the converter operates in forced ? pwm mode with fixed switching frequency and ability to sink current. fault protection of v ddq regulator during state s0 and s3, external resistor (rl1) between ocddq and v in sets the overcurrent trip threshold for the high ? side switch. an internal 31 a current sink (ioc) at ocddq pin establishes a voltage drop across this resistor and develops a voltage at the non ? inverting input of the current limit comparator. the voltage at the non ? inverting input is compared to the voltage at swddq pin when the high ? side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. when the voltage at swddq is lower than that at the non ? inverting input for 4 consecutive internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short ? to ? ground condition on swddq or vddq. the ic will be reset once vcca or vddqen is cycled. feedback compensation of v ddq regulator the compensation network is shown in figures 2 and 39. v tt active terminator in normal mode (s0) the v tt active terminator is a two ? quadrant linear regulator with two internal n ? channel power fets. it is capable of sinking and sourcing at least 1.5 a continuous current and up to 2.4 a transi ent peak current. it is activated in normal mode in state s0 when the vtten pin is high and vddq is in regulation. its input power path is from vddq with the internal fets gate drive power derived from vcca. the v tt internal reference voltage is derived from the ddqref pin. the vtt output is set to vddq/2 when v tt output is connecting to the fbvtt pin directly. this regulator is stable with only a minimum 20 f output capacitor. the v tt regulator will have an internal soft ? start when it is transited from disable to enable. during the v tt soft ? start, a current limit is used as a current source to charge up the v tt output capacitor. the current limit is initially 1.0 a during v tt soft ? start. it is then increased to 2.5 a after 128 internal clock cycles which is typically 0.32 ms. v tt active terminator in standby mode (s3) v tt output is high ? impedance in s3 mode. fault protection of v tt active terminator to provide protection for the internal fet s, bidirectional current limit is implemented, preset at the minimum of 2.5 a magnitude. thermal consideration of v tt active terminator the v tt terminator is designed to handle large transient output currents. if large currents are required for very long duration, then care should be taken to ensure the maximum junction temperature is not exceeded. the 5x6 dfn22 has a thermal resistance of 35 c/w (dependent on air flow, grade of copper, and number of vias). in order to take full advantage from this thermal capability of this package, the thermal pad underneath must be soldered directly onto a pcb metal substrate to allow good thermal contact. it is recommended that pcb with 2 oz. copper foil is used and there should have 6 to 8 vias with 0.6 mm hole size underneath the package?s thermal pad connecting the top layer metal to the bottom layer metal and the internal layer metal substrates of the pcb. vttref output the v ttref output tracks v ddqref /2 at 2% accuracy. it has source current capability of up to 15 ma. v ttref should be bypassed to analog ground of the device by 1.0 f ceramic capacitor for stable operation. the v ttref is turned on as long as v ddqref is pulled high. in s0 mode, v ttref soft ? starts with v ddq and tracks v ddqref /2. in s3 mode, v ttref is kept on with v ddq . v ttref is turned off only in s4/s5 like v ddq output. output voltages sensing the v ddq output voltage is sensed across the fbddq and agnd pins. fbddq should be connected through a feedback resistor divider to the vddq point of regulation which is usually the local v ddq bypass capacitor for load. the agnd should be connected directly through a sense trace to the remote ground sense point which is usually the ground of local v ddq bypass capacitor for load. the v tt output voltage is sensed between the fbvtt and vttgnd pins. the fbvtt should be connected to the v tt regulation point, which is usually the v tt local bypass capacitor, via a direct sense trace. the vttgnd should be connected via a direct sense trace to the ground of the v tt local bypass capacitor for load.
ncp5218 http://onsemi.com 17 supply voltage undervoltage monitor the ic continuously monitors vcca and v in through vcca pin and ocddq pin respectively. vccagd is set high if vcca is higher than its preset threshold (derived from vref with hysteresis). the ic will enter s5 state if vcca fails while in s0 and both vddqen and vtten remain high. thermal shutdown when the chip junction temperature exceeds 150 c, the entire ic is shutdown. the ic resumes normal operation only after the junction temperature dropping below 125 c. power good the pgood is an open ? drain output of a window comparator which continuously monitors the vddq output voltage. the pgood is pulled low when the vddq rises 12% above or drops 12% below the nominal regulation point. the pgood becomes high impedance when the vddq is within 12% of the preset nominal regulation voltage. a 100 k resistor is recommended to connect between pgood and vcca as pull ? up resistor for logic level output. overvoltage protection when the v ddq output is above 106% but below 130% of the nominal regulation output voltage, the controller turns of f the high ? side mosfet and turns on the low ? side mosfet to discharge the excessive output voltage. when the v ddq output voltage goes back down to the nominal regulation voltage, normal switching cycles are resumed. when the v ddq output exceeds 130% (typ) of the nominal regulation voltage for 4 consecutive internal clock cycles, the controller sets overvoltage fault, the device is latched off by turning off both the high ? side and low ? side mosfets. the overvoltage fault latch can be reset and the controller can be restarted by toggling vddqen, vcca, or vin. undervoltage protection in s3 power ? saving mode with reduced switching at lighter loads, when the v ddq falls below 94% of the nominal regulation voltage, the reduced switching frequency is raised up back to the maximum switching frequency. when v ddq voltage is back to nominal regulation voltage, the normal s3 power ? saving operation is resumed. in both s0 and s3 modes, when the v ddq falls below 65% (typ) of the nominal regulation voltage for 4 consecutive internal clock cycles, the undervoltage fault is set, the device is latched off by turning off both the high ? side and low ? side mosfets. the output is discharged by the load current. the load current and output capacitance determine the discharge rate. cycling vddqen, vcca, or v in can reset the undervoltage fault latch and restart the controller.
ncp5218 http://onsemi.com 18 vcca vddqen vtten vtten is don?t care in s5 vddq vddq soft ? start vtt vtt in h ? z vtt soft ? start vtt soft ? start pgood operating mode t hold 200 s s5 s0 s3 s0 s5 vcca goes above 4.0 v to enable the ic. vddqen goes high, vddq and vttref are enabled but not activated until vin goes above threshold of 3.0 v. vtten goes high, vtt is enabled but not activated until vddq is good. vtten goes low to activate s3 mode and to turn off vtt. both vddqen and vtten go low to trigger s5 mode; vddq, vtt, vttref are disabled, then inregddq and pgood goes low. pgood goes high. inregddq goes high, vtt goes into normal mode. vtten goes high, vtt goes into normal mode. figure 38. powerup and powerdown timing diagram vin (vocddq) vttref vin goes above the threshold, the vddq and vttref go into normal mode.
ncp5218 http://onsemi.com 19 application information input capacitor selection for v ddq buck regulator the input capacitor is important for proper regulation operation of the buck regulator. it minimizes the input voltage ripple and current ripple from the power source by providing a local loop for switching current. the input capacitor should be placed close to the drain of the high ? side mosfet and source of the low ? side mosfet with short, wide traces for connection. the input capacitor must have large enough rms ripple current rating to withstand the large current pulses present at the input of the bulk regulator due to the switching current. the required input capacitor rms ripple current rating can be estimated by the following with minimum v in : i cin(rms) i out v out v in v out v in 2 (eq. 1) besides, the voltage rating of the input capacitor should be at least 1.25 times of the maximum input voltage. capacitance of around 20 f to 50 f should be sufficient for most ddr applications. ceramic capacitors are the most suitable choice of input capacitor for notebook applications due to their low esr, high ripple current, and high voltage rating. poscap or os ? con capacitors can also be used since they have good esr and ripple current rating, but they are larger in size and more expensive. aluminum electrolytic capacitors are also a choice for their high voltage rating and low cost, but several aluminum capacitors in parallel should be used for the required ripple current. if ceramic capacitors are used, x5r and x7r types are preferred rather than the y5v type since the x5r and x7r types are ceramic capacitors and have smaller tolerance and temperature coefficient. output capacitor selection for v ddq buck regulator the output filter capacitor plays an important role in steady state output ripple voltage, load transient requirement, and loop compensation stability. the esr and the capacitance of the output capacitor are the most important parameters needed to be considered. in general, the output capacitor must have small enough esr for output ripple voltage and load transient requirement. besides, the capacitance of the output capacitor should be large enough to meet the overshoot and undershoot during load transient. since steady state output ripple voltage, transient load undershoot and overshoot are the largest at maximum v in , the esr and capacitance of output capacitor should be estimated at the maximum v in condition. for steady output ripple voltage, both esr and capacitance of the output capacitor are the contributing factors, however, the capacitor esr is the dominant factor. the output ripple voltage is calculated as follows: v ripple i l(ripple)
esr i l(ripple)
t on c out (eq. 2) v ripple i l(ripple)
esr, for small t on and large c out (eq. 3) where i l(ripple) is the inductor ripple current, t on is on ? time, and c out is the output capacitance. the inductor ripple current can be calculated by the equation: i l(ripple) (v in ? v out )
v out l
f sw
v in (eq. 4) where l is the inductance and f sw is the switching frequency. the output ripple voltage can be reduced by either using the inductor with larger inductance or the output capacitor with smaller esr. thus, the esr needed to meet the ripple voltage requirement can be obtained by: esr v ripple
l
f sw
v in (v in ? v out )
v out (eq. 5) the inductor ripple current is typically 30% of the maximum load current and the ripple voltage is typically 2% of the output voltage. thus, the above inequality can be simplified to: esr 0.02
v out 0.3
i load(max) (eq. 6) for the load transient, the output capacitor contributes to both the load ? rise and the load ? release responses. the voltage undershoot during step ? up load can be calculated by the equation: v undershoot i load
esr i load c out
1 ? v out v in f sw (eq. 7) where i load is the change in output current. if the second term is ignored, then it becomes the following inequality: esr v undershoot i load (eq. 8) the maximum esr requires to meet voltage undershoot requirement at step ? up load transient can be estimated from the above inequality. then, the required output capacitor capacitance can be obtained by the following: c out i load v undershoot ? i load
esr
1 ? v out v in f sw (eq. 9) the output voltage overshoot during load ? release is because the excessive stored energy in the inductor is absorbed by the output capacitor. the overshoot voltage can be calculated by the following equation: v overshoot li 2 step(peak) c out v 2 out c out ? v out (eq. 10)
ncp5218 http://onsemi.com 20 then the required output capacitor capacitance can be estimated by: c out l
i 2 step(peak) (v overshoot v out ) 2 ? v 2 out (eq. 11) i step(peak) i load (v in ? v out )
v out 2l
f sw
v in (eq. 12) where i step(peak) is the load current step plus half of the ripple current at the load release and i load is the change in the output load current. besides, the esr and the capacitance of the output filter capacitor also contribute to double pole and esr zero frequencies of the output filter, and the poles and zeros frequencies of the compensation network for close loop stability. the compensation network will be discussed in more detail in the loop compensation section. other parameters about output filter capacitor that needed to be considered are the voltage rating and ripple current rating. the voltage rating should be at least 1.25 times the output voltage and the rms ripple current rating should be greater than the inductor ripple current. thus, the voltage rating and ripple current rating can be obtained by: v rating 1.25
v out (eq. 13) i cout(rms) i l(ripple) (v in ? v out )
v out l
f sw
v in (eq. 14) sp ? cap, poscap and os ? con capacitors are suitable for the output capacitor since their esr is low enough to meet the ripple voltage and load transient requirements. usually, two or more capacitors of the same type, capacitance and esr can be used in parallel to achieve the required esr and capacitance without change the esr zero position for maintaining the same loop stability. other than the performance point of view, the physical size and cost are also the concerned factors for output capacitor selection. inductor selection the inductor should be chosen according to the inductor ripple current, inductance, maximum current rating, transient load release, and dcr. in general, the inductor ripple current is 20% to 40% of the maximum load current. a ripple current of 30% of the maximum load current can be used as a typical value. the required inductance can be estimated by: l (v in ? v out )
v out 0.3
i load(max)
v in
f sw (eq. 15) where i load(max) is the maximum load current. the dc current rating of the inductor should be about 1.2 times of the peak inductor current at maximum output load current. therefore, the maximum dc current rating of the inductor can be obtained by: i l(rating) 1.2
i l(peak) (eq. 16) where i l(peak) is the peak inductor current at maximum load current which is determined by: i l(peak) i load(max) i l(ripple) 2 (eq. 17) i load(max) (v in ? v out )
v out 2
l
f sw
v in since the excessive energy stored in the inductor contributed to the output voltage overshoot during load release, the following inequality can be used to ensure that the selected inductance value can meet the voltage overshoot requirement at load release: l c out
( (v overshoot v out ) 2 ? v 2 out ) i 2 step(peak) (eq. 18) in addition, the inductor also needs to have low enough dcr to obtain good conversion efficiency. in general, inductors with about 2.0 m to 3.0 m per h of inductance can be used. besides, larger inductance value can be selected to achieve higher efficiency as long as it still meets the targeted voltage overshoot at load release and inductor dc current rating. moreover, it should be noted that using too small inductance value will cause very large inductor ripple current in ccm in s0 mode and extremely large peak inductor current in dcm in power ? saving mode during s3 mode. for both cases, output capacitors with smaller esr and larger capacitance are required to keep the output ripple voltage small. it should also be noted that the peak inductor current under dcm light ? load condition in power ? saving mode in s3 mode will be larger than the peak inductor current under heavy ? load condition in s0 mode when very small inductance value is used. besides, using smaller inductance will achieve lower efficiency and require larger minimum load to maintain nominal voltage regulation in power ? saving mode in s3 state. therefore, it is recommended that the inductance value should be at least 0.56 h or above to obtain optimum performance. mosfet selection external n ? channel mosfets are used as the switching elements of the buck controller. both high ? side and low ? side mosfets must be logic ? level mosfets which can be fully turned on at 5.0 v gate ? drive voltage. on ? resistance (r ds(on) ), maximum drain ? to ? source voltage (v dss ), maximum drain current rating, and gate charges (q g , q gd , q gs ) are the key parameters to be considered when choosing the mosfets. for on ? resistance, it should be the lower; the better is the performance in terms of efficiency and power dissipation. check the mosfet?s rated r ds(on) at v gs = 4.5 vwhen selecting the mosfets. the low ? side mosfet should have lower r ds(on) than the high ? side mosfet since the
ncp5218 http://onsemi.com 21 turn ? on time of the low ? side mosfet is much longer than the high ? side mosfet in high v in and low v out buck converter. generally, high ? side mosfet with r ds(on) about 7.0 m and low ? side mosfet with r ds(on) about 5.0 m can achieve good efficiency. the maximum drain current rating of the high ? side mosfet and low ? side mosfet must be higher than the peak inductor current at maximum load current. the low ? side mosfet should have larger maximum drain current rating than the high ? side mosfet since the low ? side mosfet have longer turn ? on time. the maximum drain ? to ? source voltage rating of the mosfets used in buck converter should be at least 1.2 times of the maximum input voltage. generally, v dss of 30 v should be sufficient for both high ? side mosfet and low ? side mosfet of the buck converter for notebook application. as a general rule of thumb, the gate charges are the smaller; the better is the mosfet while r ds(on) is still low enough. mosfets are susceptible to false turn ? on under high dv/dt and high vds conditions. under high dv/dt and high v ds condition, current will flow through the c gd of the capacitor divider formed by c gd and c gs , cause the c gs to charge up and the v gs to rise. if the v gs rises above the threshold voltage, the mosfet will turn on. therefore, it should be checked that the low ? side mosfet have low q gd to q gs ratio. this indicates that the low ? side mosfet have better immunity to short moment false turn ? on due to high dv/dt during the turn ? on of the high ? side mosfet. such short moment false turn ? on will cause minor shoot ? through current which will degrade efficiency, especially at high input voltage condition. overcurrent protection of vddq buck regulator the ocp circuit is configured to set the current limit for the current flowing through the high ? side fet and inductor during s0 and s3. the overcurrent tripping level is programmed by an external resistor rl1 connected between the ocddq pin and drain of the high ? side fet. an internal 31 a current sink (ioc) at pin ocddq establishes a voltage drop across the resistor rl1 at a magnitude of rl1xioc and develops a voltage at the non ? inverting input of the current limit comparator. another voltage drop is established across the high ? side mosfet r ds(on) at a magnitude of i l xr ds(on) and a voltage is developed at swddq when the high ? side mosfet is turned on and the inductor current flows through the r ds(on) of the mosfet. the voltage at the non ? inverting input of the current limit comparator is then compared to the voltage at swddq pin when the high ? side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. when the voltage at swddq is lower than the voltage at the non ? inverting input of the current limit comparator for four consecutive internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short ? to ? ground condition on swddq or v ddq . i.e., the voltage drop across the r ds(on) of high ? side fet developed by the drain current is larger than the voltage drop across rl1, the ocp is triggered and the device will be latched off. the overcurrent protection will trip when a peak inductor current hit the i limit determined by the equation: i limit rl1
ioc r ds(on) (eq. 19) it should be noted that the ocddq pin must be pulled high to vin through a resistor rl1 and this pin cannot be left floating for normal operation. the voltage drop across rl1 must be less than 1.0 v to allow enough headroom for the voltage detection at the ocddq pin under low vin condition. in addition, since the mosfet r ds(on) varies with temperature as current flows through the mosfet increases, the ocp trip point also varies with the mosfet r ds(on) temperature variation. since the ioc and r ds(on) have device variations and mosfet r ds(on) increase with temperature, to avoid false triggering the overcurrent protection in normal operating output load range, calculate the rl1 value from the previous equation with the following conditions such that minimum value of inductor current limit is set: 1. the minimum ioc value from the specification table. 2. the maximum r ds(on) of the mosfet used at the highest junction temperature. 3. determine i limit for i limit > i load(max) + i l(ripple)/ 2, where i load(max) = i vddq(max) + i vtt(max) if vtt is powered by vddq. besides, a decoupling capacitor c dcpl should be added closed to the lead of the current limit setting resistor rl1 which connected to the drain of the high ? side mosfet. loop compensation once the output lc filter components have been determined, the compensation network components can be selected. since ncp5218 is a voltage mode pwm converter with output lc filter, type iii compensation network is required to obtain the desired close loop bandwidth and phase boost with unconditional stability. the ncp5218 pwm modulator, output lc filter and type iii compensation network are shown in figure 39. the output lc filter has a double pole and a single zero. the double pole is due to the inductance of the inductor and capacitance of the output capacitor, while the single zero is due to the esr and capacitance of the output capacitor. the type iii compensation has two rc pole ? zero pairs. the two zeros are used to compensate the lc double pole and provide 180 phase boost. the two poles are used to compensate the esr zero and provide controlled gain roll ? off. for an ideally compensated system, the bode plot should have the close ? loop gain roll ? off with a slope of ? 20 db/decade crossing the 0 db with the required bandwidth and the phase margin larger than 45 for all frequencies below the 0 db frequency. the closed loop
ncp5218 http://onsemi.com 22 gain is obtained by adding the modulator and filter gain (in db) to the compensation gain (in db) . the bandwidth is the frequency at which the gain is 0 db and the phase margin is the difference between the close loop phase and 180 . the goal of compensation is to achieve a stable close loop system with the highest possible bandwidth, the gain having ? 20 db/decade slope at 0 db gain crossing, and sufficient phase margin for stability. the bandwidth of close loop gain should be less than 50% of the switching frequency and the compensation gain should be bounded by the error amplifier open loop gain. adaptive ramp osc vddq pwm logic a pwm comp vin pgnd vref tgddq swddq bgddq pgnd comp fbddq vddq l c2 c1 r3 c3 r4 r2 r1 cout vin q2 q1 cin error amp vboost ncp5218 esr output filter compensation network modulator vccp vramp figure 39. voltage mode buck converter with modulator, lc filter and type iii compensation modulator dc gain can be calculated by: g mod(dc) 20 log v in v ramp (eq. 20) lc filter double pole and esr zero break frequencies are defined by: f plc 1 2
l
c out (eq. 21) f zesr 1 2
esr
c out (eq. 22) compensation network dc gain can be calculated by the equation: g comp(dc) 20 log r 3 r 1 (eq. 23) type iii compensation poles and zeros break frequencies are defined by the below equations: f z1 1 2
r 3
c 2 (eq. 24) f p1 1 2
r 3
c 1
c 2 c 1 c 2 (eq. 25) f z2 1 2
(r 1 r 4 )
c 3 (eq. 26) f p2 1 2
r 4
c 3 (eq. 27) 80 100 open loop error amp gain compensation gain closed loop gain 60 40 20 0 ? 20 ? 40 ? 60 gain (db) 10 100 1 k 10 k 100 k 1 m 10 m f z1 f z2 f p1 f p2 f zesr f plc modulator & filter gain 20 log 20 log r 3 r 1 v in v ramp frequency (hz) figure 40. asymptotic bode plot of the converter gain
ncp5218 http://onsemi.com 23 close loop system bandwidth can be calculated by: bw r 3 r 1
v in v ramp
1 2
l
c out (eq. 28) since the ramp amplitude of the pwm modulator has a voltage feedforward function, the ramp amplitude is a function of v in which can be determined by: v ramp 1.25 v 0.045
(v in ? 5.0 v) (eq. 29) below are some guidelines for setting the compensation components: 1. set a value for r 1 between 2.0 k and 5.0 k . 2. set a target for the close loop bandwidth which should be less than 50% and is typically 1/8 to 1/4 of the switching frequency. 3. pick compensation dc gain (r 3 /r 1 ) for desired close loop bandwidth. 4. place 1st zero at half filter double pole. 5. place 1st pole at esr zero. 6. place 2nd zero at filter double pole. 7. place 2nd pole at half the switching frequency. by using the above equations and guidelines, the compensation components values can be determined by the equations below: r 3 2
bw
v ramp
r 1
l
c out v in (eq. 30) c 2 2
l
c out r 3 (eq. 31) c 1 c 2 r 3
c 2 esr
c out 1 (eq. 32) r 4 r 1
f sw
l
c out 1 (eq. 33) c 3 1
r 4
f sw (eq. 34) the modulator and filter gain, compensation gain, and close loop gain asymptotic bode plot can be drawn by the calculated results to check the compensation gain and close loop gain obtained. an example of asymptotic bode plot is shown in figure 40. the phase of the output filter can be calculated by: phase (filter) ? tan ? 1 (2 f
esr
c out ) ? tan ? 1 2 f
esr dcr
c out ( 2 f ) 2
l
c out ? 1 (eq. 35) where the dcr of the inductor can be neglected if the dcr is small. the phase of the type iii compensation network can be calculated by: phase (typeiii) ? 90 tan ? 1 (2 f
r 3
c 2 ) ? tan ? 1 2 f
r 3
c 1
c 2 c 1 c 2 (eq. 36) tan ? 1 (2 f
(r 1 r 4 )
c 3 ) ? tan ? 1 (2 f
r 4
c 3 ) the close loop phase can be calculated by summing the filter phase and compensation phase: phase (closeloop) phase (filter) phase (typeiii) (eq. 37) then the close loop phase margin can be estimated by: phase (margin) phase (closeloop) ( 180 ) (eq. 38) it should be checked that closed loop gain has a 0 db gain crossing with ? 20 db/decade slope and a phase margin of 45 or greater. the compensation components values may require some adjustment to meet these requirements. besides, the compensation gain should be checked with the error amplifier open loop gain to make sure that it is bounded by the error amplifier open loop gain. the poles and zeros locations and hence the compensation network components values may need to be further fine tuned after actual system testing and analysis. feedback resistor divider the output voltage of the buck regulator can be adjusted by the feedback resistor divider formed by r 1 and r 2 . once the value of r 1 is selected when determining the compensation components, the value of r 2 can be obtained by: r 2 0.8
r 1 v out ? 0.8 (eq. 39) it is recommended to adjust the value of r 2 to fine ? tune the output voltage when it is necessary. the value of r 1 should not be changed since the compensation dc gain and the 2 nd zero break frequency of the compensation gain are contributed by r 1 . if the value of r 1 is changed, the compensation, the close loop bandwidth and phase margin, and the system stability will be affected. besides, it is recommended to use resistors with at least 1% tolerance for r 1 and r 2 . soft ? start of buck regulator a v ddq soft ? start feature is incorporated in the device to prevent surge current from power supply and output voltage overshoot during power up. when vddqen, vcca, and vocddq rise above their respective upper threshold voltages, the external soft ? start capacitor c ss will be charged up by a constant current source, i ss . when the soft ? start voltage (vcss) rises above the ss_en voltage ( 50 mv), the bgddq and tgddq will start switching and v ddq output will ramp up with vfbddq following the soft ? start voltage. when the soft ? start voltage reaches the ss_ok voltage ( v ref + 50 mv), the soft ? start of
ncp5218 http://onsemi.com 24 v ddq is finished. the c ss will continue to charge up until it reaches about 2.5 v to 3.0 v. the soft ? start time t ss can be programmed by the soft ? start capacitor according to the following equation: t ss 0.8
c ss i ss (eq. 40) ceramic capacitors with low tolerance and low temperature coefficient, such as b, x5r, x7r ceramic capacitors are recommended to be used as the c ss . ceramic capacitors with y5v temperature characteristic are not recommended. soft ? start of vtt active terminator the vtt source current limit is used as a constant current source to charge up the vtt output capacitor during vtt soft ? start. besides, the vtt source current limit is reduced to about 1.0 a for 128 internal clock cycles to minimize the inrush current during vtt soft ? start. therefore, the vtt soft ? start time t ssvtt can be estimated by the equation: t ssvtt c outvtt
vtt i limvtss (eq. 41) where c outvtt is the capacitance of vtt output capacitor and i limvtss is the vtt soft ? start source current limit. boost supply diode and capacitor an external diode and capacitor are used to generate the boost voltage for the supply of the high ? side gate driver of the bulk regulator. schottky diode with low forward voltage should be used to ensure higher floating gate drive voltage can be applied across the gate and the source of the high ? side mosfet. a schottky diode with 30 v reverse voltage and 0.5 a dc current ratings can be used as the boost supply diode for most applications. a 0.1 f to 0.22 f ceramic capacitor should be sufficient as the boost capacitor. vtti input power supply for vtt and vttr both vtt and vttr are supplied by vtti for sourcing current. vtti is normally connected to the vddq output for optimum performance. if vtti is connected to vddq, no bypass capacitor is required to add to vtti since the bulk capacitor at vddq output is sufficiently large. besides, the maximum load current of vddq is the sum of i vddq(max) and i vtt(max) when making electrical design and components selection of the vddq buck regulator. vtti can also be connected to an external voltage source. however, extra power dissipation will be generated from the internal vtt high ? side mosfet and more heatsinking is required if the external voltage is higher than vddq. whereas, the headroom will be limit by the r ds(on) of the vtt linear regulator high ? side mosfet, and the maximum vtt output current with vtt within regulation window will also be reduced if the external voltage is lower than vddq. besides, the vtti pin input must be bypassed to vttgnd with at least a 10 f capacitor if external voltage source is used. design example a design example of a v ddq bulk converter with the following design parameters is shown below: ddr2 v ddq bulk converter design parameters: 1. input voltage range: 7.0 v to 20 v. 2. nominal v out : 1.8 v. 3. static tolerance: 2% ( 36 mv). 4. transient tolerance: 100 mv. 5. maximum output current: 10 a (i vddq(max) = 8.0 a, i vtt(max) = 2.0 a). 6. load transient step: 1.0 a to 8.0 a. 7. switching frequency: 400 khz. 8. bandwidth: 100 khz. 9. soft ? start time: 400 s. a. calculate input capacitor rms ripple current rating and voltage rating: i cin(rms) 10 a
1.836 v 8.0 v 1.836 v 8.0 v 2 4.2 a (eq. 42) v cin(rating) 20
1.25 v 25 v (eq. 43) therefore, two 10 f 25 v ceramic capacitors with 1210 size in parallel are used. b. calculate inductance, rated current and dcr of inductor: first, suppose ripple current is 0.3 times the maximum output current, such that: l (20 v ? 1.836 v)
1.836 v 0.3
10 a
20 v
400 khz 1.39 h (eq. 44) second, the overshoot requirement at load release is then considered and supposes two 220 f capacitors in parallel are used as an initially guess, such that: l 440 f
( (100 mv 1.836 v) 2 ? (1.836 v) 2 ) 7a 0.3
7a 2 2 2.56 h (eq. 45) thus, inductors with standard inductance values of 1.5 h, 1.8 h and 2.2 h can be used. as a trade ? off between smaller overshoot and better efficiency, the average value of 1.8 h inductor is selected. then, the maximum rated dc current is calculated by: i l(rated) 1.2
10 a (20 v ? 1.836 v)
1.836 v 2
1.8 h
400 khz
20 (eq. 46) 13.39 a therefore, inductor with maximum rated dc current of 14 a or larger can be used. finally, the dcr of inductor is 2.0 m per h of inductance as a rule of thumb, then: dcr 2m 1 h
1.8 h 3.6 m (eq. 47)
ncp5218 http://onsemi.com 25 thus, inductor with 1.8 h inductance, 14 a maximum rated dc current and 3.5 m dcr is chosen. c. calculate esr and capacitance of output filter capacitor: first, the esr required to achieve the desired output ripple voltage is considered. suppose the output ripple voltage is 2% of the nominal output voltage. esr (0.02
1.8 v)
1.8 h
400 khz
20 v (20 v ? 1.8 v)
1.8 v (eq. 48) 15.8 m second, the esr required to meet the transient load undershoot requirement is considered, such that: esr 100 mv 7a 14.3 m (eq. 49) therefore, the suitable esr is 12 m or smaller, and the value of 7.5 m is selected for more design margin and better performance. then, two same sp ? caps or poscaps each with 15 m esr in parallel having a resultant esr of 7.5 m should be good enough to meet the requirements. then, check that whether the previously supposed capacitance meets the undershoot and overshoot requirements. to ensure that undershoot requirement of less than 100 mv is achieved, the capacitance must be: c out 7a 100 mv ? 7a
7.5 m
1 ? 1.8 v ? 36 mv 20 v 400 khz 335.9 f (eq. 50) to make sure that overshoot requirement of less than 100 mv is fulfilled, capacitance must be: c out 1.8 h
7a (20 v ? 1.836 v)
1.836 v 2
1.8 h
400 khz
20 v 2 (100 mv 1.836 v) 2 ? (1.836 v) 2 317.6 f (eq. 51) therefore, output capacitor with capacitance of 440 f should meet both undershoot and overshoot requirements. sometimes, it may take several times of iterations between the process of selecting inductance of the inductor and esr and capacitance of the output capacitor. then, the voltage rating of the output capacitor is estimated by: v rated 1.25
1.836 v 2.3 v (eq. 52) thus, output capacitor with 2.5 v or larger rated voltage is used. finally, the rated rms ripple current of the output capacitor is considered: i cout(rms) (20 v ? 1.836 v)
1.836 v 1.8 h
400 khz
20 v 2.3 a (eq. 53) thus, capacitor with rated rms ripple current of 3.0 a or larger should be selected. two capacitors each with 1.5 a rated ripple current can be connected in parallel to provide a total of 3.0 a rated rms ripple current. therefore, two same capacitors in parallel each with capacitance of 220 f, esr of 15 m , rated voltage of 2.5 v, and rated rms ripple current of 1.5 a are used. d. calculate the resistance value of ocp current limit setting resistor: first, the ocp current limit is estimated at maximum load condition, such that: i limit 8a 2a (20 v ? 1.836 v)
1.836 v 2
1.8 h
400 khz
20 v (eq. 54) 11.16 a thus, i limit is set to 1 1.5 a. suppose from the high ? side mosfet data sheet, the maximum r ds(on) is 10 m . then, the value of rl1 is calculated by: rl1 11.5 a
10 m 26 a 4.4 k (eq. 55) therefore, the resistor with standard value of 4.7 k is selected for rl1. e. calculate the rc values of the compensation network: first, 4.3 k is chosen as the value of r 1 which is in the range between 2.0 k and 5.0 k since the worst case of stability is at the maximum v in , the close loop compensation should be considered at maximum v in . then the ramp amplitude can be calculated as below: v ramp 1.25 v 0.045
(20 v ? 5v) 1.925 v (eq. 56) since the l = 1.8 h, c out = 440 f, and the target close loop bandwidth is 100 khz, the value of r 3 can be calculated as: r 3 2
100 khz
1.925 v
4.3 k
1.8 h
440 f 20 v 7.3 k (eq. 57)
ncp5218 http://onsemi.com 26 thus, standard value of 7.5 k is selected for r 3 . if the first zero break frequency is placed at half the lc filter?s double pole, the value of c 2 can be calculated by: c 2 2
1.8 h
440 f 7.5 k 7.5 nf (eq. 58) thus, standard value of 8.2 nf is chosen for c2. if the 1st pole break frequency is placed at the lc filter?s esr zero, the value of c 1 can be calculated by: c 1 8.2 nf 464.9 pf (eq. 59) 7.5 k
8.2 nf 7.5 m
440 f 1 thus, standard value of 470 pf can be chosen for c 1 . however, 180 pf is selected for more phase boost at the 0 db gain crossing. then, if the second zero break frequency is placed at the lc filter?s double pole and the second pole is placed at half the switching frequency, the value of r 4 can be calculated by: r 4 4.3 k
400 khz
1.8 h
440 f ? 1 125 (eq. 60) thus, standard value of 130 is selected for r 4 . then, c 3 can be calculated by: c 3 1
130
400 khz 6.12 nf (eq. 61) therefore, standard value of 5.6 nf is selected for c 3 . then, the close loop phase margin can be estimated by the following: phase (typeiii) ? 90 tan ? 1 (2
100 khz
7.5 k
8.2 nf) (eq. 62) ? tan ? 1 2
100 khz
7.5 k
180 pf
8.2 nf 180 pf 8.2 nf tan ? 1 (2
100 khz
(4.3 k 130 )
5.6 nf) ? tan ? 1 (2
100 khz
130
5.6 nf) 20.57 phase (filter) ? tan ? 1 (2
100 khz
7.5 m
440 f) ? tan ? 1 2
100 khz
7.5 m ( 2
100 khz ) 2
1.8 h
440 f ? 1 ? 150.47 phase (closeloop) ? 150.47 20.57 ? 129.90 phase (margin) phase (closeloop) ? ( ? 180 ) ? 129.90 ? ( ? 180 ) 50.10 therefore, the phase margin is large enough for stability. f. calculate the resistance value of feedback resistor divider: since a 4.3 k resistor is chosen as the high ? side resistor r 1 , the resistance value of low ? side resistor r 2 can be calculated by: r 2 0.8
4.3 k 1.8 v ? 0.8 v 3.44 k (eq. 63) therefore, a 3.44 k resistor is selected for the low ? side feedback resistor r 2 . g. calculate soft ? start capacitor value for the desired 400 s vddq soft ? start time: c ss 4.0 a
400 s 0.8 v 2.0 nf (eq. 64) therefore, 2.0 nf x5r ceramic capacitor is selected for the soft ? start capacitor.
ncp5218 http://onsemi.com 27 pcb layout guidelines cautious pcb layout design is very critical to ensure high performance and stable operation of the ddr power controller. the following items must be considered when preparing pcb layout: 1. all high ? current traces must be kept as short and wide as possible to reduce power loss. high ? current traces are the trace from the input voltage terminal to the drain of the high ? side mosfet, the trace from the source of the high ? side mosfet to the inductor, the trace from inductor to the v ddq output terminal, the trace from the input ground terminal to the v ddq output ground terminal, the trace from v ddq output to vtti pin, the trace from vtt pin to v tt output terminal, and the trace from v tt output ground terminal to the vttgnd pin. power handling and heaksinking of high ? current traces can be improved by also routing the same high ? current traces in the other layers and joined together with multiple vias. 2. power components which include the input capacitor, high ? side mosfet, low ? side mosfet and v ddq output capacitor of the buck converter section must be positioned close together to minimize the current loop. the input capacitor must be placed close to the drain of the high ? side mosfet and the source of the low ? side mosfet. 3. to ensure the proper function of the device, separated ground connections should be used for different parts of the application circuit according to their functions. the input capacitor ground, the low ? side mosfet source, the v ddq output capacitor ground, the vccp decoupling capacitor ground should be connected to the pgnd. the trace path connecting the source of the low ? side mosfet and pgnd pin should be minimized. the v tt output capacitor ground should be connected to the vttgnd first with a short trace, it is then connected to the ground plane of pgnd. the vcca decoupling capacitor ground, the ground of the v ddq feedback resistor, the soft ? start capacitor ground, the vttref output capacitor ground should be connected to the agnd. the agnd pin is then connected directly through a sense trace to the remote ground sense point of the pgnd, which is usually the ground of the local bypass capacitor for the load. never connect the agnd, pgnd and vttgnd together just under the thermal pad. 4. the thermal pad of the dfn22 package should be connected to the ground planes in the internal layer and bottom layer from the copper pad at top layer underneath the package through six to eight vias with 0.6 mm hole ? diameter to help heat dissipation and ensure good thermal capability. it is recommended to use pcb with 1 oz or 2 oz copper foil. the thermal pad can be connected to either pgnd ground plane or agnd ground plane but not both. 5. the input capacitor ground terminal, the v ddq output capacitor ground terminal and the source of the low ? side mosfet must be connected to the pgnd ground plane through multiple vias. 6. sensitive traces like trace from fbddq, trace from comp, trace from ocddq, trace from fbvtt and trace from vttref should be avoided from the high ? voltage switching nodes like swddq, boost, tgddq and bgddq. 7. separate sense trace should be used to connect the v ddq point of regulation, which is usually the local bypass capacitor for load, to the feedback resistor divider to ensure accurate voltage sensing. the feedback resistor divider should be place close to the fbddq pin. 8. separate sense trace should be used to connect the v tt point of regulation, which is usually the local bypass capacitor for load, to the fbvtt pin. 9. separate sense trace should be used to connect the v ddq point of regulation to the ddqref pin to ensure that the reference voltage to v tt is accurately half of the v ddq voltage. 10. the traces length between the gate driver outputs and gates of the mosfets must be minimized to avoid parasitic impedance. 11. to ensure normal function of the device, an rc filter should be placed close to the vcca pin and a decoupling capacitor should be placed close to the vccp pin. 12. the copper trace area of the switching node which includes the source of the high ? side mosfet, drain of the low ? side mosfet and high voltage side of the inductor should be minimized by using short wide trace to reduce emi. 13. a snubber circuit consists of a 3.3 resistor and 1.0 nf capacitor may need to be connected across the switching node and pgnd to reduce the high ? frequency ringing occurring at the rising edge of the switching waveform to obtain more accurate inductor current limit sensing of the v ddq buck converter. however, adding this snubber circuit will slightly reduce the conversion efficiency. 14. vtti should be connected to v ddq output with wide and short trace if v ddq is used as the sourcing supply for v tt . an input capacitor of at least 10 f should be added close to the vtti pin and bypassed to vttgnd if external voltage supply is used as the v tt sourcing supply.
ncp5218 http://onsemi.com 28 1 2 d1 mbr0530t1 l1 r9 10 k r11 4.3 k c2 c14 100 pf c12 c15 2.2 nf c4 1 f c5 (option) c8 c3 c1 1.8 nf c6 c7 c13 c11 low?esr poscap tpe series sanyo 4tpe150mi c11, c12 panasonic eefud0g151r low esr sp?cap ud series c9 (option for vin < 8 v) r12 3.44 k * r4 100 k bias supply (4.5 v to 24 v) 1.8 v/10 a q1 ntms4700n n?channel q2 ntms4107n n?channel c10 tp1 tp2 tp8 vddq tp5 tp6 vin 5 v tp7 gnd jp3 jp2 vcca vddq r10 130 tp3 tp9 vddqgnd tp4 vref 5 v r6 c16 4.7 nf r7 r8 2.5 v/12 a vddqen 1 vtten 2 3 ss 4 pgood 15 vtt 6 fbvtt 8 vttgnd 5 vcca 11 ddqref 10 agnd 9 ocddq 16 vccp 20 boost 17 tgddq 18 swddq 19 bgddq 21 pgnd 22 comp 12 fbddq 13 vtti 7 on semiconductor ncp5218 thpad 23 vttref 14 u1 ncp5218 c17 c18 0.9 v/15 ma jp4 1.25 v/15 ma r13 tp10 agnd (option) r14 c19 1 nf (option) (option) c20 (option) vttgnd jp1 figure 41. schematic diagram of evaluation board r5 10 f 10 f 10 1 f 10 f 1.25 v/ 1.5 a 0.9 v/ 1.5 a r3 100 k r2 100 k r1 100 k 0.1 f 4.7 f 0.1 f 0 0 10 f *33 f 150 f 150 f 1 f (150 f, 4 v, 15 m ) (150 f, 4 v, 18 m ) 0 10 f 10 f 30 v, 7.3 m 30 v, 4.7 m 1.8 h, 14 a, 3.4 m * install r12 = 3.44 k for vddq = 1.8 v install r12 = 2.02 k for vddq = 2.5 v fpwm 3.3 5.6 k vtt vttgnd pgood
ncp5218 http://onsemi.com 29 pcb layout of evaluation board figure 42. silkscreen of evaluation board pcb figure 43. top layer of evaluation board pcb layout figure 44. middle layer1 of evaluation board pcb layout figure 45. middle layer2 of evaluation board pcb layout figure 46. bottom layer of evaluation board pcb layout
ncp5218 http://onsemi.com 30 table 2. bill of materials of the evaluation board item qty designators part description mfg. & p/n remark 1 1 c1 capacitor, ceramic, 1.8 nf/50 v 0603 panasonic ecj1vb1h182k 2 2 c2, c17 capacitor, ceramic, 10 f/6.3 v 0805 panasonic ecj2fb0j106m 3 2 c3, c20 capacitor, ceramic, 10 f/6.3 v 0805 panasonic ecj2fb0j106m c3 & c20 are optional 4 3 c4, c13, c18 capacitor, ceramic, 1 f/10 v 0805 panasonic ecj1vb1a105m 5 2 c5, c7 capacitor, ceramic, 0.1 f/25 v 0603 panasonic ecj1vb1e104k c5 is optional 6 1 c6 capacitor, ceramic, 4.7 f/10 v 0603 panasonic ecj2fb1c475m 7 2 c8, c10 capacitor, ceramic, 10 f/25 v 1210 panasonic ecj4yb1e106m 8 1 c9 capacitor, electrolytic, 33 f/35 v size d panasonic eevfk1v330p c9 is optional 9 2 c11, c12 capacitor, sp ? cap, 150 f/4 v size d / capacitor, poscap, 150 f/4 v size d panasonic eefud0g151r / sanyo 4tpe150mi 10 1 c14 capacitor, ceramic, 100 pf/50 v 0603 panasonic ecj1vc1h101k 11 1 c15 capacitor, ceramic, 2.2 nf/50 v 0603 panasonic ecj1vb1h222k 12 1 c16 capacitor, ceramic, 4.7 nf/50 v 0603 panasonic ecj1vb1h472k 13 1 c19 capacitor, ceramic, 1 nf/50 v 0603 panasonic ecj1vb1h102k c19 is optional 14 1 d1 diode, 0.5 a 30 v schottky sod ? 123 on semiconductor mbr0530t1 15 3 jp1, jp2, jp3 header, 3 ? pin, 100 mil spacing any 16 1 jp4 header, 2 ? pin, 100 mil spacing any 17 1 l1 inductor, smd, 1.8 h/14 a / inductor, smd, 1.5 h/17 a panasonic etqp2h1r8bfa / toko fda1055 ? 1r5m=p3 18 1 q1 mosfet, n ? channel so ? 8, 30 v/14.5 a on semiconductor ntms4700n 19 1 q2 mosfet, n ? channel so ? 8, 30 v/19 a on semiconductor ntms4107n 20 4 r1, r2, r3, r4 resistor, 100 k 5% 0603 panasonic erj3geyj104v 21 1 r5 resistor, 10 5% 0603 panasonic erj3geyj100v 22 1 r6 resistor, 5.6 k 1% 0603 panasonic erj3ekf5602v 23 1 r7 resistor, 0 5% 0603 panasonic erj3geyj0r0v 24 2 r8, r13 resistor, 0 5% 0603 panasonic erj3geyj0r0v 25 1 r9 resistor, 10 k 1% 0603 panasonic erj3ekf1002v 26 1 r10 resistor, 130 1% 0603 panasonic erj3ekf1300v 27 1 r11 resistor, 4.3 k 1% 0603 panasonic erj3ekf4301v 28 1 r12 resistor, 3.44 k 1% 0603 panasonic erj3ekf3441v 29 1 r14 resistor, 3.3 5% 0603 panasonic erj3geyj3r3v r14 is optional 30 8 tp1 ? tp8 header, single pin any 31 1 u1 2 ? in ? 1 notebook ddr power controller on semiconductor ncp5218 32 4 shunt, 100 mil jumper any 33 1 test pin, 0.7 mm diameter, 12 mm height any place at the gnd between c11 and c8 34 4 bumpon, 4.44 x 0.20 transparent 3m 35 1 4 ? layered pcb 2500 mil x 2000 mil any
ncp5218 http://onsemi.com 31 package dimensions dfn22 mn suffix case 506af ? 01 issue a c 0.15 e2 d2 l b 22 x a d notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to plated terminals and is measured between 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. e c e a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 3.98 4.28 e 5.00 bsc e2 2.98 3.28 e 0.50 bsc k 0.20 ??? l 0.50 0.60 c 0.15 pin 1 location a1 (a3) seating plane c 0.08 c 0.10 22 x k 22 x a 0.10 b c 0.05 c note 3 111 12 22 top view side view bottom view 0.280 0.011 mm inches scale 8:1 0.980 0.039 4.300 0.169 5.770 0.227 3.130 0.123 0.500 0.020 0.340 0.013 20x 22x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scil lc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different ap plications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical ex perts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemn ify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp5218/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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